Lithography is employed in semiconductor manufacturing to pattern features in a photoresist. A layer of photoresist is exposed to incident light, which may be deep-ultraviolet (DUV) radiation, mid-ultraviolet (MUV) radiation, or X-ray radiation. Alternately, the layer of photoresist may be exposed to energetic electron in e-beam lithography. The energy of the photons or electrons causes changes in chemical composition of exposed portions of the photoresist, for example, by cross-linkage, scission, side chain removal, etc. Pre-baking or post-baking of the photoresist may be employed to maximize the changes in the chemical properties of the exposed portion of the photoresist relative to unexposed portions of the photoresist.
The exposed photoresist is developed to remove one of the set of exposed portions of the photoresist and the set of unexposed portions of the photoresist relative to the other. The photoresist is classified as a positive photoresist or a negative photoresist depending on the nature of the chemical changes upon exposure. If the photoresist becomes chemically less stable upon exposure, the photoresist is a positive photoresist. If the photoresist becomes chemically more stable upon exposure, the photoresist is a negative photoresist. In case a positive photoresist is employed, the exposed portions of the positive photoresist are removed upon development. In case a negative photoresist is employed, the unexposed portions of the negative photoresist are removed upon development.
A developed photoresist comprises a lithographic pattern. The features of the lithographic pattern have dimensions that are the same as, or greater than, a “minimum feature size,” which is also called a “critical dimension.” The minimum feature size is a function of a lithography tool employed to form the lithographic pattern. The minimum feature size F that a projection system can print is given approximately by:F=k×λ/NA,where k is a coefficient that reflects tool specific proportionality constant reflecting the efficiency of the lithography system and other process related factors, λ is the wavelength of the light employed for radiation, and NA is the numerical aperture of the lens. Typically, the value of the coefficient k is in the range of about 0.5.
While the minimum feature size is defined only in relation to a lithography tool and normally changes from generation to generation of semiconductor technology, it is understood that the minimum feature size, i.e., the critical dimension, is to be defined in relation to the best performance of lithography tools available at the time of semiconductor manufacturing. The minimum feature sizes include a minimum line width and a minimum line spacing for a nested line pattern, and a minimum via hole diameter for a nested via hole pattern. In general, the minimum feature sizes vary depending on the geometry of the features to be printed on a photoresist. Given geometry and given a specific lithography tool, however, minimum feature sizes are defined as a quantifiable number. Further, since the minimum achievable wavelength is determined by the type of the light source in commercially available lithography tools, for given geometry, the minimum feature sizes may be defined based on the technological capabilities at any given time. As of 2008, the minimum feature sizes are about 50 nm and are expected to shrink in the future. Any dimension less than the lithographic minimum dimension is called a “sublithographic dimension.”
The pattern in the developed photoresist is subsequently transferred into an underlying layer employing the developed photoresist and an etch mask. Thus, the dimensions of features that may be formed in a semiconductor structure are directly tied to the dimensions of features in the developed photoresist. The minimum pitch of a repetitive lithographic pattern is the twice the minimum feature size since each unit pattern includes a line and a space or a via hole and a surrounding spacer.
Standard lithographic methods form patterns having lithographic dimensions, i.e., dimensions that are greater than the minimum feature size. Each generation of lithography tools thus impose a limitation on the width, spacing, and the pitch of a lithographic pattern. Such limitations are an inherent limit on the size of unit cells of an array of semiconductor devices. For example, static random access memory (SRAM) devices, dynamic random access memory (DRAM) devices, and flash memory devices employ an array of unit cells.
Such a unit cell typically employs features at or near the minimum feature size, which is enabled by the lithography tool employed in the manufacturing process. Frequently, the array of the unit cell employs a two-dimensional array of contact vias and a one dimensional array of conductive lines to maximize the wiring density. For example, the array of the unit cell may comprise a two-dimensional array of substrate contact vias, a one dimensional array of first metal lines, a two-dimensional array of first conductive vias above the first metal lines, a one dimensional array of second metal lines, etc.
An exemplary prior art wiring structure is shown in FIG. 1. The exemplary prior art wiring structure comprises an array of the unit cell, an array of contact vias 160, and an array of conductive lines 170. The conductive vias 160 may be located beneath the conductive lines 170, or above the conductive lines 170. The conductive vias 160 are arranged in a two-dimensional array so that the conductive vias 160 have a first lithographic pitch LP1′, which is a pitch that may be formed by lithographic methods, and have a first lithographic spacing LS1′, which is a spacing that may be formed by lithographic methods. The first lithographic spacing LS1′ is the same as the first lithographic pitch LP1′ less the dimension of a conductive via 160 in the direction of the measurement of the first lithographic pitch LP1′. The array of the conductive vias 160 may have another lithographic pitch in another direction, which may, or may not, be perpendicular to the direction of the first lithographic pitch LP1′. Likewise, the array of the conductive vias 160 may have another lithographic spacing in the other direction.
The conductive lines 170 are arranged in a one-dimensional array so that the conductive lines 170 have a second lithographic pitch LP2′, which is a pitch that may be formed by lithographic methods, and have a second lithographic spacing LS2′, which is a spacing that may be formed by lithographic methods. The second lithographic spacing LS2′ is the same as the second lithographic pitch LP2′ less the dimension of a conductive line 170 in the direction of the measurement of the second lithographic pitch LP2′. The first lithographic pitch LP1′ and the second lithographic pitch LP2′ are along the same direction and commensurate. Particularly, the first lithographic pitch LP1′ and the second lithographic pitch LP2′ are the same.
Successful fabrication of the exemplary semiconductor structures in FIG. 1 and fabrication of any wiring structure in general requires control of overlay in between the pattern of the conductive vias 160 and the conductive lines in the direction of the first lithographic pitch LP1′. Failure to control overlay between the printed pattern of the conductive vias 160 and the conductive lines 170 results in electrical short and/or electrical opens, rendering the array of semiconductor devices non-functional. “Overlay budget” for lithography is therefore one of the limiting factors in scaling semiconductor devices.
In view of the above, there exists a need for a method of forming wiring structures that provide greater overlay tolerance, and yet provide functional wiring for an array of semiconductor devices.
Further, there exists a need to locally manipulate lithographic images to increase overlay budget so that wiring density may be increased and scaling down of dimensions of semiconductor devices may be facilitated without risking electrical shorts or electrical opens.